Signal integrity is crucial in digital design because system speeds and clock edge rates continue to increase. To improve signal integrity, both single-ended and differential signals should be properly terminated. Termination can be implemented with external termination resistors on a board, or with on-chip termination technology. Figure 1 compares the integrity of a signal without termination against one using Altera's Stratix^® II device on-chip termination.

Figure 1. Stratix II Device On-Chip Termination Improves Signal Integrity

Stratix II devices support both on-chip termination and external termination schemes, as shown in Table 1.

On-Chip and Off-Chip Termination Benefits

On-chip termination eliminates the need for external resistors and simplifies the design of a PCB; Stratix II device on-chip termination benefits are described in Table 2.

Termination with external resistors, on the other hand, provides tighter tolerance and is recommended for designs with stringent impedance tolerance requirements. Altera provides an external termination design kit with recommendations for low-cost, small-form factor resistor packs, board schematics and layout examples, along with simulation and test results. Figure 2 shows how off-chip termination is implemented using resistor packs.

Figure 2. Off-Chip Termination Using Resistor Packs

Series Termination

Stratix II devices support on-chip series termination for LVTTL, LVCMOS, SSTL-18, and SSTL-2 single-ended I/O standards (shown in Table 3). The on-chip termination is provided at the output signal to match the impedance of the transmission line, typically 25 or 50Ω. You can use this termination in many general-purpose applications and to interface with DDR SDRAM memories.

Table 3. Supported I/O Standards for Series Termination
Standard	Resistance ( )
3.3-V, 2.5-V, 1.8-V, 1.5-V LVTTL	25 or 50
3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS	25 or 50
SSTL-18, SSTL-2 (Class I)	25
SSTL-18, SSTL-2 (Class II)	25

Parallel Termination

Stratix II devices support on-chip parallel termination for SSTL and HSTL single-ended I/O standards (refer to Table 4). The on-chip parallel termination can be set to 50Ω. You can use this termination when implementing interfaces with external memories such as the DDR SDRAM and QDRII SRAM memories.

Stratix II devices support parallel termination through external resistors. Altera provides an external termination design kit with recommendations for low-cost, small-form factor resistor packs, board schematics and layout examples, along with simulation and test results.

Differential Termination

You use differential termination in system applications that require support for high-speed interface protocols, such as SPI-4.2, SFI-4, XSBI, RapidIO™, HyperTransport™, NPSI, and UTOPIA IV standards.

Stratix II devices support LVDS and HyperTransport input on-chip differential termination. The value of the on-chip termination resistor, R_D, shown in Figure 3 is 100Ω.

Figure 3. On-Chip Differential Termination

Related Links

• Parallel I/O Technology Center

Figure 1. Jitter in Clock Signals

This deviation in a clock’s output transition from its ideal position can negatively impact data transmission quality. In many cases, other signal deviations, like signal skew and coupled noise are combined and labeled as jitter.

Deviation (expressed in ±ps) can occur on either the leading edge or the trailing edge of a signal. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies.

Excessive jitter can increase the bit error rate (BER) of a communications signal by incorrectly transmitting a data bit stream. In digital systems, jitter can lead to a violation of timing margins, causing circuits to behave improperly. Accurate measurement of jitter is necessary for ensuring the reliability of a system.

Sources of Jitter

Common sources of jitter include:

• Internal circuitry of the phase-locked loop (PLL)
• Random thermal noise from a crystal
• Other resonating devices
• Random mechanical noise from crystal vibration
• Signal transmitters
• Traces and cables
• Connectors
• Receivers

Beyond these sources, termination dependency, cross talk, reflection, proximity effects, VCC sag, ground bounce, and electromagnetic interference (EMI) from nearby devices and equipment can also increase the amount of jitter in a device.

Reflection and cross-talk frequency-dependent effects may be amplified if an adjacent signal is synchronous and in phase. Aside from noise caused by power supplies and ground, changes in circuit impedance are responsible for most of the jitter in data transmission circuits.

Jitter Components

The two major components of jitter are random jitter, and deterministic jitter.

Random Jitter

The random component in jitter is due to the noise inherent in electrical circuits and typically exhibits a Gaussian distribution. Random jitter (RJ) is due to stochastic sources, such as substrate and power supply. Electrical noise interacts with the slew rate of signals to produce timing errors at the switching points.

RJ is additive as the sum of squares, and follows a bell curve. Since random jitter is not bounded, it is characterized by its standard deviation (rms) value.

Deterministic Jitter

Deterministic jitter (DJ) is data pattern dependant jitter, attributed to a unique source. Sources are generally related to imperfections in the behavior of a device or transmission media but may also be due to power supply noise, cross-talk, or signal modulation.

DJ is linearly additive and always has a specific source. This jitter component has a non-Gaussian probability density function and is always bounded in amplitude. DJ is characterized by its bounded, peak-to-peak, value.

Types of Jitter

There are many different types of jitter. Period jitter, cycle-to-cycle jitter and half-period jitter are described below.

Period Jitter

Period jitter is the change in a clock’s output transition (typically the rising edge) from its ideal position over consecutive clock edges. Period jitter is measured and expressed in time or frequency. Period jitter measurements are used to calculate timing margins in systems, such as tSU and tCO.

Cycle-to-Cycle Jitter

Cycle-to-cycle jitter is the difference in a clock’s period from one cycle to the next. Cycle-to-cycle jitter is the most difficult to measure usually requiring a timing interval analyzer.

As shown in Figure 2, J1 and J2 are the measured jitter values. The maximum value measured over multiple cycles is the maximum cycle-to-cycle jitter.

Figure 2. Cycle-to-Cycle Jitter

Half-Period Jitter

Half-period jitter is the measure of maximum change in a clock’s output transition from its ideal position during one-half period. Figure 3 illustrates half-period jitter.

Half-period jitter impacts DDR transfer applications by reducing capture margins.

Figure 3. Half-Period Jitter

Jitter Specifications

The performance of the PLL is measured using several parameters. Three of the common specifications used to characterize the PLL are jitter generation, tolerance, and transfer.

Jitter Generation

Jitter generation is the measure of the intrinsic jitter produced by the PLL and is measured at its output. Jitter generation is measured by applying a reference signal with no jitter to the input of the PLL, and measuring its output jitter. Jitter generation is usually specified as a peak-to-peak period jitter value.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock in the presence of jitter of various magnitudes at different frequencies) when jitter is applied to its reference. Jitter tolerance is usually specified using an input jitter mask.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various bandwidth settings. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for low frequency input jitter signals than for high frequency ones. Jitter transfer is typically specified using a bandwidth plot.

References

Lecroy. 2001. Jitter & Timing Analysis Training Presentation.